UVM Agent

UVM Agent

用户自定义的agent 应该从 uvm_agent 扩展而来，uvm_agent 继承于 uvm_component 。

代理通常包含驱动程序、定序器和监视器（a driver, a sequencer, and a monitor）

代理可以配置为主动或被动（ active or passive）

Active agent

active agent 产生激励并驱动 DUT

一个active agent 应该由driver、sequencer和monitor三个组件组成

Passive agent

Passive agents对 DUT 信号进行采样但不驱动它

Passive agents仅由monitor组成

可以使用 set config 方法将 agent 配置为 ACTIVE/PASSIVE，默认 agent 是 ACTIVE。设置配置可以在env或test中完成。

set_config_int("path_to_agent", "is_active", UVM_ACTIVE);
set_config_int("path_to_agent", "is_active", UVM_PASSIVE);

get_is_active() Method

get_is_active() 如果代理充当主动代理，则返回 UVM_ACTIVE，如果代理充当被动代理，则返回 UVM_PASSIVE。

Writing UVM Agent

1.通过扩展UVM_agent写一个agent，

class mem_agent extends uvm_agent;
 
  // UVM automation macros for general components
  `uvm_component_utils(mem_agent)
 
  // constructor
  function new (string name, uvm_component parent);
    super.new(name, parent);
  endfunction : new
 
endclass : mem_agent

2. 声明driver、sequencer和monitor实例，

//declaring agent components
mem_driver    driver;
mem_sequencer sequencer;
mem_monitor   monitor;

3. 根据agent类型，在构建阶段创建agent组件，driver和sequencer只为活动agent创建。

// build_phase
function void build_phase(uvm_phase phase);
  super.build_phase(phase);
 
  if(get_is_active() == UVM_ACTIVE) begin
    driver = mem_driver::type_id::create("driver", this);
    sequencer = mem_sequencer::type_id::create("sequencer", this);
  end
 
  monitor = mem_monitor::type_id::create("monitor", this);
endfunction : build_phase

4.将driver 的seq_item_port连接到sequencer seq_item_export，用于连接阶段driver和sequencer之间的通信。

// connect_phase
function void connect_phase(uvm_phase phase);
  if(get_is_active() == UVM_ACTIVE) begin
    driver.seq_item_port.connect(sequencer.seq_item_export);
  end
endfunction : connect_phase

完整的agent 代码：

class mem_agent extends uvm_agent;
  //declaring agent components
  mem_driver    driver;
  mem_sequencer sequencer;
  mem_monitor   monitor;
 
  // UVM automation macros for general components
  `uvm_component_utils(mem_agent)
 
  // constructor
  function new (string name, uvm_component parent);
    super.new(name, parent);
  endfunction : new
 
  // build_phase
  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
 
    if(get_is_active() == UVM_ACTIVE) begin
      driver = mem_driver::type_id::create("driver", this);
      sequencer = mem_sequencer::type_id::create("sequencer", this);
    end
 
    monitor = mem_monitor::type_id::create("monitor", this);
  endfunction : build_phase
 
  // connect_phase
  function void connect_phase(uvm_phase phase);
    if(get_is_active() == UVM_ACTIVE) begin
      driver.seq_item_port.connect(sequencer.seq_item_export);
    end
  endfunction : connect_phase
 
endclass : mem_agent